(a) Field of the Invention
The present invention relates to a method for manufacturing a MOS (metal oxide semiconductor) transistor. More particularly, the present invention relates to a method for manufacturing a MOS transistor in which a silicon nitride layer is formed to prevent impurities from a pre-metal dielectric layer from diffusing into the transistor.
(b) Description of the Related Art
There are two general classes of field effect transistors (FETs), and they include the MOSFET and the JFET (junction FET). The present invention is related to the MOSFET, which typically includes the electrodes of a source, a drain, and a gate on a semiconductor substrate. Metal interconnect lines are connected to upper areas of the source, drain, and gate to enable the application of electrical signals to the same. The areas where such connections are made are referred to as contacts.
To enable ohmic contact of each of the electrodes, that is, to minimize the resistance of each of the electrodes, silicide films are formed between the metal interconnect lines; and each electrode of the source, drain, and gate. Also, a silicon nitride film is deposited over an entire upper surface of the transistor including on the silicide films. The silicon nitride film acts as an etch stop layer during etching to form contacts and to prevent the diffusion of impurities from a BPSG (boron phosphorous silicate glass) layer into other elements.
A conventional method for manufacturing a MOS transistor will be described with reference to FIGS. 1a through 1c. 
Referring first to FIG. 1a, oxide layer 3 as a gate oxide and polysilicon for use as a gate electrode 4 are formed at a predetermined width on a surface of a device region of a silicon wafer 1. The device region of the silicon wafer 1 is defined by a field oxide layer 2, which is formed by a LOCOS (local oxidation of silicon) process or a trench process. Next, using the gate electrode 4 as a mask, ion injection using a p-type or n-type dopant at a low concentration is performed on the device region of the silicon wafer 1. As a result, LDDs (lightly doped drains) 5 are formed on the device region of the silicon wafer 1, and side walls 6 are formed to both sides of the gate oxide layer 3 and the gate electrode 4.
Following this operation, a conducting dopant identical to that used for the LDDs 5 is ion-injected at a high concentration on the device region of the silicon wafer 1 using the side walls 6 and the gate electrode 4 as a mask to thereby form a source/drain 7. A titanium silicide layer 8 is then formed on the source/drain 7 and also on the gate electrode 4 to reduce a contact resistance.
Subsequently, with reference to FIG. 1b, in order to form a liner layer that acts as an etch stop layer during etching to form contacts and also acts to prevent the diffusion of impurities from a BPSG layer into other elements, a silicon nitride layer 9 is formed over all exposed elements formed on the silicon wafer 1. The silicon nitride layer 9 is formed by PECVD (plasma enhanced chemical vapor deposition) and at a temperature of approximately 400 Å.
A large amount of approximately 20˜30 mol % of hydrogen generated in the decomposition process of silane and ammonia is contained in the silicon nitride layer 9. The hydrogen reacts with a BPSG layer formed in a subsequent process to ionize impurities. That is, the large amount of hydrogen contained in the silicon nitride layer 9 formed by PECVD exists in various forms such as combined with silicon (Si—H, Si—H2, Si—H3) and combined with nitrogen (N—H, NH2). The cohesive strength when combined with silicon, and particularly in Si—H, is especially weak such that these elements are easily separated when receiving an external chemical shock.
Subsequently, with reference to FIG. 1c, a BPSG layer 10 is formed as a pre-metal dielectric layer on the silicon nitride layer 9. The BPSG layer 10 is formed to a thickness of approximately 14,000 Å using SACVD (subatmospheric CVD) and at a temperature of 500° C. To increase the strength of the BPSG layer 10, heat treating is performed at 700° C. to realize densification.
With respect to the BPSG layer 10 prior to densification, the bond between boron and oxygen (B—O), phosphorus and oxygen (P—O), and silicon and oxygen (Si—O) is weak such that it is easily broken by external chemical and/or mechanical shock. Therefore, the BPSG layer 10 is densified to increase (by approximately three times) its chemical and mechanical strength.
However, with the formation of the BPSG layer 10, Si—H makes contact with the B—O, P—O, and Si—O to react with the same in a state where the Si—H close to the surface of the silicon nitride layer 9 receives the thermal energy of the 500° C. used to deposit the BPSG layer such that its cohesive strength weakens. As a result, hydrogen combines with oxygen, and boron ions (B+), phosphorous ions (P+), and silicon ions (Si+) are generated.
The boron ions, in particular, diffuse into the silicon nitride layer 9 because of their small atomic radius and superior mobility. As a result, the boron ions exist on the interfacial surface of the titanium silicide layer 8 or are left remaining within the silicon nitride layer 9 such that the boron ions diffuse into the silicon wafer 1 during the heat treating process to perform densification of the BPSG layer 10.
Boron diffused in this manner, and in particular, in the PMOS using boron as impurities of the source and drain, acts to reduce the threshold voltage of the same. It is also possible for the boron to cause current leakage. That is, a channel is not removed even with the elimination of an applied voltage for the removal of a gate channel, and the channel is instead weakly formed to thereby cause current leakage.
Conventional arts related to such diffusion are disclosed in U.S. Pat. Nos. 6,475,847, and 6,420,752.